VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator

TL;DR

This paper introduces a reconfigurable vectorwise hardware accelerator for spiking neural networks, achieving high power efficiency and low latency on edge devices through novel model and hardware design innovations.

Contribution

It presents a binary weight SNN model with IF-based Batch Normalization and a reconfigurable hardware accelerator supporting multi-bit inputs and model flexibility.

Findings

Achieves 25.9 TOPS/W power efficiency.

Maintains competitive accuracy on MNIST and CIFAR-10 with only 8 time steps.

Reduces memory bandwidth with a two-layer fusion mechanism.

Abstract

Spiking neural networks (SNNs) that enable low-power design on edge devices have recently attracted significant research. However, the temporal characteristic of SNNs causes high latency, high bandwidth and high energy consumption for the hardware. In this work, we propose a binary weight spiking model with IF-based Batch Normalization for small time steps and low hardware cost when direct training with input encoding layer and spatio-temporal back propagation (STBP). In addition, we propose a vectorwise hardware accelerator that is reconfigurable for different models, inference time steps and even supports the encoding layer to receive multi-bit input. The required memory bandwidth is further reduced by two-layer fusion mechanism. The implementation result shows competitive accuracy on the MNIST and CIFAR-10 datasets with only 8 time steps, and achieves power efficiency of 25.9 TOPS/W.