BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention

TL;DR

This paper introduces a lightweight super resolution hardware accelerator with pixel attention, achieving high-quality image reconstruction at real-time speeds using minimal parameters and efficient design.

Contribution

It presents a novel hardware-efficient pixel attention mechanism integrated into a super resolution accelerator, reducing complexity and memory access while improving image quality.

Findings

Achieves 0.38dB better PSNR than FSRCNN

Supports full HD at 30 fps

Uses only 25.9K parameters with simple structure

Abstract

Increasingly, convolution neural network (CNN) based super resolution models have been proposed for better reconstruction results, but their large model size and complicated structure inhibit their real-time hardware implementation. Current hardware designs are limited to a plain network and suffer from lower quality and high memory bandwidth requirements. This paper proposes a super resolution hardware accelerator with hardware efficient pixel attention that just needs 25.9K parameters and simple structure but achieves 0.38dB better reconstruction images than the widely used FSRCNN. The accelerator adopts full model block wise convolution for full model layer fusion to reduce external memory access to model input and output only. In addition, CNN and pixel attention are well supported by PE arrays with distributed weights. The final implementation can support full HD image reconstruction at 30 frames per second with TSMC 40nm CMOS process.