Wafer-scale nanofabrication of telecom single-photon emitters in silicon

TL;DR

This paper demonstrates a scalable, wafer-scale method for fabricating telecom single-photon emitters in silicon, enabling the development of large-scale quantum photonic integrated circuits for quantum computing.

Contribution

It introduces a controllable, scalable fabrication process for single G and W centers in silicon using focused ion beams and CMOS-compatible broad-beam implantation.

Findings

Achieved >50% probability of creating single-photon emitters at desired locations.

Developed a CMOS-compatible implantation protocol for scalable fabrication.

Paved the way for industrial-scale quantum photonic processors.

Abstract

A highly promising route to scale millions of qubits is to use quantum photonic integrated circuits (PICs), where deterministic photon sources, reconfigurable optical elements, and single-photon detectors are monolithically integrated on the same silicon chip. The isolation of single-photon emitters, such as the G centers and W centers, in the optical telecommunication O-band, has recently been realized in silicon. In all previous cases, however, single-photon emitters were created uncontrollably in random locations, preventing their scalability. Here, we report the controllable fabrication of single G and W centers in silicon wafers using focused ion beams (FIB) with a probability exceeding 50%. We also implement a scalable, broad-beam implantation protocol compatible with the complementary-metal-oxide-semiconductor (CMOS) technology to fabricate single telecom emitters at desired positions on the nanoscale. Our findings unlock a clear and easily exploitable pathway for industrial-scale photonic quantum processors with technology nodes below 100 nm.