Automatic Datapath Optimization using E-Graphs
Samuel Coward, George A. Constantinides, Theo Drane

TL;DR
This paper introduces an automated RTL datapath optimization method using E-Graphs and graph rewriting, achieving significant area reductions and generating multiple optimized architectures, streamlining the design process.
Contribution
It presents a novel automated approach leveraging E-Graphs for RTL optimization, capturing complex transformations and extending prior optimization techniques.
Findings
Achieves up to 71% reduction in circuit area.
Automatically reproduces typical manual optimizations.
Generates a library of optimized designs based on operand width.
Abstract
Manual optimization of Register Transfer Level (RTL) datapath is commonplace in industry but holds back development as it can be very time consuming. We utilize the fact that a complex transformation of one RTL into another equivalent RTL can be broken down into a sequence of smaller, localized transformations. By representing RTL as a graph and deploying modern graph rewriting techniques we can automate the circuit design space exploration, allowing us to discover functionally equivalent but optimized architectures. We demonstrate that modern rewriting frameworks can adequately capture a wide variety of complex optimizations performed by human designers on bit-vector manipulating code, including significant error-prone subtleties regarding the validity of transformations under complex interactions of bitwidths. The proposed automated optimization approach is able to reproduce the…
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Taxonomy
TopicsLow-power high-performance VLSI design · VLSI and FPGA Design Techniques · VLSI and Analog Circuit Testing
