Multiplier with Reduced Activities and Minimized Interconnect for Inner Product Arrays

TL;DR

This paper introduces a pipelined inner product multiplier using online digit-serial arithmetic with reduced activity and interconnect, achieving significant area and power savings for various bit precisions.

Contribution

It proposes a novel pipelined multiplier design that employs online digit-serial arithmetic with truncated precision to reduce power and area consumption.

Findings

Up to 38% power reduction compared to non-truncated designs.

Up to 44% area reduction over conventional multipliers.

Effective for 8 to 32-bit precisions.

Abstract

We present a pipelined multiplier with reduced activities and minimized interconnect based on online digit-serial arithmetic. The working precision has been truncated such that $p<n$ bits are used to compute $n$ bits product, resulting in significant savings in area and power. The digit slices follow variable precision according to input, increasing upto $p$ and then decreases according to the error profile. Pipelining has been done to achieve high throughput and low latency which is desirable for compute intensive inner products. Synthesis results of the proposed designs have been presented and compared with the non-pipelined online multiplier, pipelined online multiplier with full working precision and conventional serial-parallel and array multipliers. For $8, 16, 24$ and $32$ bit precision, the proposed low power pipelined design show upto $38\%$ and $44\%$ reduction in power and area respectively compared to the pipelined online multiplier without working precision truncation.