L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime

TL;DR

This paper introduces L2C2, a novel NV memory-based LLC design with compression and wear leveling, along with a detailed forecast procedure to analyze its lifetime and performance evolution.

Contribution

It presents a new LLC architecture for NV memory that combines fault tolerance, compression, and wear leveling, plus a method to accurately forecast its lifetime and performance.

Findings

L2C2 extends effective capacity lifetime by up to 37 times.

Compression reduces write rate, enhancing cache lifetime.

The forecast procedure accurately models temporal evolution of NV-LLC.

Abstract

Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecast procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50\% of the effective capacity is degraded, depending on the variability in the manufacturing process.