Characterization and Optimization of Integrated Silicon-Photonic Neural Networks under Fabrication-Process Variations

TL;DR

This paper models the impact of fabrication-process variations on silicon-photonic neural networks and proposes a design-time optimization to significantly improve their accuracy and robustness.

Contribution

It introduces the first model of FPV effects on SPNNs and a novel optimization method to enhance MZI tolerance, reducing accuracy loss due to fabrication variations.

Findings

Optimized MZIs improve accuracy by up to 93.95% on MNIST.

The method reduces accuracy loss to below 0.5%.

Low area overhead makes it suitable for resource-constrained designs.

Abstract

Silicon-photonic neural networks (SPNNs) have emerged as promising successors to electronic artificial intelligence (AI) accelerators by offering orders of magnitude lower latency and higher energy efficiency. Nevertheless, the underlying silicon photonic devices in SPNNs are sensitive to inevitable fabrication-process variations (FPVs) stemming from optical lithography imperfections. Consequently, the inferencing accuracy in an SPNN can be highly impacted by FPVs -- e.g., can drop to below 10% -- the impact of which is yet to be fully studied. In this paper, we, for the first time, model and explore the impact of FPVs in the waveguide width and silicon-on-insulator (SOI) thickness in coherent SPNNs that use Mach-Zehnder Interferometers (MZIs). Leveraging such models, we propose a novel variation-aware, design-time optimization solution to improve MZI tolerance to different FPVs in SPNNs. Simulation results for two example SPNNs of different scales under realistic and correlated FPVs indicate that the optimized MZIs can improve the inferencing accuracy by up to 93.95% for the MNIST handwritten digit dataset -- considered as an example in this paper -- which corresponds to a <0.5% accuracy loss compared to the variation-free case. The proposed one-time optimization method imposes low area overhead, and hence is applicable even to resource-constrained designs