Quantum computing hardware for HEP algorithms and sensing

TL;DR

This paper explores superconducting quantum hardware architectures tailored for high energy physics algorithms, discussing their capabilities, challenges, and future prospects to advance quantum computing applications in HEP.

Contribution

It introduces and compares two promising superconducting quantum architectures for HEP algorithms, highlighting their potential, challenges, and strategies for error correction.

Findings

Demonstrated HEP algorithms on superconducting architectures

Identified challenges and future opportunities for quantum hardware in HEP

Reviewed error correction strategies for improved performance

Abstract

Quantum information science harnesses the principles of quantum mechanics to realize computational algorithms with complexities vastly intractable by current computer platforms. Typical applications range from quantum chemistry to optimization problems and also include simulations for high energy physics. The recent maturing of quantum hardware has triggered preliminary explorations by several institutions (including Fermilab) of quantum hardware capable of demonstrating quantum advantage in multiple domains, from quantum computing to communications, to sensing. The Superconducting Quantum Materials and Systems (SQMS) Center, led by Fermilab, is dedicated to providing breakthroughs in quantum computing and sensing, mediating quantum engineering and HEP based material science. The main goal of the Center is to deploy quantum systems with superior performance tailored to the algorithms used in high energy physics. In this Snowmass paper, we discuss the two most promising superconducting quantum architectures for HEP algorithms, i.e. three-level systems (qutrits) supported by transmon devices coupled to planar devices and multi-level systems (qudits with arbitrary N energy levels) supported by superconducting 3D cavities. For each architecture, we demonstrate exemplary HEP algorithms and identify the current challenges, ongoing work and future opportunities. Furthermore, we discuss the prospects and complexities of interconnecting the different architectures and individual computational nodes. Finally, we review several different strategies of error protection and correction and discuss their potential to improve the performance of the two architectures. This whitepaper seeks to reach out to the HEP community and drive progress in both HEP research and QIS hardware.