Characterizing Error Mitigation by Symmetry Verification in QAOA

TL;DR

This paper develops a theoretical framework and empirical analysis of symmetry verification in QAOA, showing it improves fidelity and solution quality under realistic noise conditions on superconducting and ion-trap quantum processors.

Contribution

It introduces a theoretical model for symmetry verification under local noise and demonstrates its effectiveness on MaxCut problems and real hardware, highlighting practical error mitigation benefits.

Findings

Symmetry verification improves QAOA fidelity under certain noise regimes.

On IonQ hardware, symmetry verification enhances the QAOA objective by up to 19.2%.

Theoretical formulas predict fidelity improvements for problems with global Z2 symmetry.

Abstract

Hardware errors are a major obstacle to demonstrating quantum advantage with the quantum approximate optimization algorithm (QAOA). Recently, symmetry verification has been proposed and empirically demonstrated to boost the quantum state fidelity, the expected solution quality, and the success probability of QAOA on a superconducting quantum processor. Symmetry verification uses parity checks that leverage the symmetries of the objective function to be optimized. We develop a theoretical framework for analyzing this approach under local noise and derive explicit formulas for fidelity improvements on problems with global $\mathbb{Z}_2$ symmetry. We numerically investigate the symmetry verification on the MaxCut problem and identify the error regimes in which this approach improves the QAOA objective. We observe that these regimes correspond to the error rates present in near-term hardware. We further demonstrate the efficacy of symmetry verification on an IonQ trapped ion quantum processor where an improvement in the QAOA objective of up to 19.2\% is observed.