Mars: Near-Optimal Throughput with Shallow Buffers in Reconfigurable Datacenter Networks
Vamsi Addanki, Chen Avin, Stefan Schmid

TL;DR
This paper introduces Mars, a reconfigurable datacenter network topology that achieves near-optimal throughput with shallow buffers by emulating regular graphs, addressing buffer constraints that limit existing high-throughput designs.
Contribution
Mars is a novel periodic reconfigurable topology that emulates regular graphs to optimize throughput under buffer and delay constraints, unlike prior complete graph emulations.
Findings
Mars outperforms existing systems in throughput with bounded buffers.
Emulating regular graphs reduces buffer requirements compared to complete graphs.
Systematic analysis of degree d optimizes throughput given buffer and delay constraints.
Abstract
The performance of large-scale computing systems often critically depends on high-performance communication networks. Dynamically reconfigurable topologies, e.g., based on optical circuit switches, are emerging as an innovative new technology to deal with the explosive growth of datacenter traffic. Specifically, \emph{periodic} reconfigurable datacenter networks (RDCNs) such as RotorNet (SIGCOMM 2017), Opera (NSDI 2020) and Sirius (SIGCOMM 2020) have been shown to provide high throughput, by emulating a \emph{complete graph} through fast periodic circuit switch scheduling. However, to achieve such a high throughput, existing reconfigurable network designs pay a high price: in terms of potentially high delays, but also, as we show as a first contribution in this paper, in terms of the high buffer requirements. In particular, we show that under buffer constraints, emulating the…
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Taxonomy
TopicsInterconnection Networks and Systems · Advanced Memory and Neural Computing · Graphene research and applications
