Selectively biased tri-terminal vertically-integrated memristor configuration
Vasileios Manouras, Spyros Stathopoulos, Alex Serb, and Themis, Prodromakis

TL;DR
This paper introduces a vertically stacked memristor configuration with a shared middle electrode, enabling selective control and enhanced memory states, which improves reconfigurable electronics and device protection.
Contribution
It presents a novel tri-terminal vertically integrated memristor design with a shared middle electrode, allowing selective switching and improved resistive state control.
Findings
Separate device switching affects the entire system non-linearly.
The configuration increases the number of distinguishable resistive states.
Simultaneous reset reduces reset time in larger arrays.
Abstract
Memristors, when utilized as electronic components in circuits, can offer opportunities for the implementation of novel reconfigurable electronics. While they have been used in large arrays, studies in ensembles of devices are comparatively limited. Here we propose a vertically stacked memristor configuration with a shared middle electrode. We study the compound resistive states presented by the combined in-series devices and we alter them either by controlling each device separately, or by altering the full configuration, which depends on selective usage of the middle floating electrode. The shared middle electrode enables a rare look into the combined system, which is not normally available in vertically stacked devices. In the course of this study it was found that separate switching of individual devices carries over its effects to the complete device (albeit non-linearly), enabling…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Neuroscience and Neural Engineering · Transition Metal Oxide Nanomaterials
