FT-EALU: Fault Tolerant Arithmetic and Logic Unit for Critical Embedded and Real time Systems
Athena Abdi, Sina Shahoveisi

TL;DR
This paper introduces FT-EALU, a fault-tolerant arithmetic and logic unit for embedded systems that uses data diversification, weighted voting, and a design-time learning scheme to effectively mitigate transient and permanent faults.
Contribution
The paper presents a novel fault-tolerant approach combining data diversification, weighted voting, and a learning scheme to improve fault correction in embedded ALUs.
Findings
Corrects approximately 85% of single-bit permanent faults.
Corrects approximately 70% of double-bit permanent faults.
Demonstrates efficiency through experimental validation.
Abstract
In this paper, a fault-tolerant approach to mitigate transient and permanent faults of arithmetic and logic operations of embedded processors called FT-EALU is proposed. In this method, each operation is replicated in time and the derived final results are voted to generate the final output. To consider the effect of permanent faults, replicating identical operations in time is not sufficient, and diversifying the operands is required. To this aim in FT-EALU, we consider three distinct versions of input data and apply the target operation to them serially in time. To avoid high time overhead, we employ simple operators such as shift and swap to make an appropriate diversion in input data. Our proposed fault tolerance approach passes the replicated and diverse results to a novel weighted voter that is designed based on the reward/punishment strategy. For each version of execution, based…
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Taxonomy
TopicsRadiation Effects in Electronics · Parallel Computing and Optimization Techniques · Distributed systems and fault tolerance
