PLCverif: Status of a Formal Verification Tool for Programmable Logic Controller

TL;DR

PLCverif is an open-source formal verification tool for PLC control logic, enhancing safety and correctness in industrial automation systems, with improved language support and integration since its initial release.

Contribution

The paper introduces PLCverif, a formal verification platform for PLCs, detailing its capabilities, improvements since 2019, and its open-source release process.

Findings

Expanded support for Siemens PLC programming languages

Enhanced integration with CBMC backend

Open-source release enabling wider adoption

Abstract

Programmable Logic Controllers (PLC) are widely used for industrial automation including safety systems at CERN. The incorrect behaviour of the PLC control system logic can cause significant financial losses by damage of property or the environment or even injuries in some cases, therefore ensuring their correct behaviour is essential. While testing has been for many years the traditional way of validating the PLC control system logic, CERN developed a model checking platform to go one step further and formally verify PLC logic. This platform, called PLCverif, first released internally for CERN usage in 2019, is now available to anyone since September 2020 via an open source licence. In this paper, we will first give an overview of the PLCverif platform capabilities before focusing on the improvements done since 2019 such as the larger support coverage of the Siemens PLC programming languages, the better support of the C Bounded Model Checker backend (CBMC) and the process of releasing PLCverif as an open-source software.