Highly-Multiplexed Superconducting Detector Readout: Approachable High-Speed FPGA Design

TL;DR

This paper introduces a high-speed, highly-multiplexed superconducting detector readout system implemented on an FPGA, achieving increased detector capacity with reduced power and accessible design methods.

Contribution

The work presents a novel FPGA-based readout system for superconducting detectors that doubles capacity and simplifies FPGA design using high-level tools, with open-source implementation.

Findings

Reads out 2,048 detectors at 512 MHz

Uses 80% less power than previous schemes

Leverages open-source FPGA design tools

Abstract

This work presents the design and preliminary performance of a highly-multiplexed superconducting detector readout. The readout system is implemented on the Xilinx ZCU111 RFSoC Evaluation Board. The current design uses 12% of the DSPs, 60% of the LUTs, 20% of the FFs, and 30% of the BRAM and makes timing at 512 MHz. The system uses two integrated ADCs and DACs running at 4.096 GSPS to read out 2,048 superconducting detectors. This work targets a 2x increase in the number of superconducting detectors processed per board with 80% less power than previous readout schemes. The open-source design leverages modern FPGA productivity tools including Vivado High-Level Synthesis to create all custom IP blocks, PYNQ to test and verify individual IP and develop Python drivers, and Vivado ML Intelligent Design Runs to close timing. We emphasize strategies for achieving timing closure without custom HDL which we expect to be useful for superconducting device groups looking to utilize FPGAs in high-performance applications without specialized knowledge in FPGA design.