100 Gb/s High Throughput Serial Protocol (HTSP) for Data Acquisition Systems with Interleaved Streaming

TL;DR

This paper introduces a high-throughput 100 Gb/s serial protocol leveraging FPGA hard IP blocks to efficiently support interleaved streaming in data acquisition systems, reducing complexity and physical links.

Contribution

It presents a novel protocol design that utilizes FPGA hard IP blocks for robust, low latency data transport with interleaved streams, minimizing programmable logic use.

Findings

Achieves 100 Gb/s data rate with low latency

Reduces programmable logic overhead in FPGA implementations

Supports interleaved streaming for data acquisition systems

Abstract

Demands on Field-Programmable Gate Array (FPGA) data transport have been increasing over the years as frame sizes and refresh rates increase. As the bandwidths requirements increase the ability to implement data transport protocol layers using "soft" programmable logic becomes harder and start to require harden IP blocks implementation. To reduce the number of physical links and interconnects, it is common for data acquisition systems to require interleaving of streams on the same link (e.g. streaming data and streaming register access). This paper presents a way to leverage existing FPGA harden IP blocks to achieve a robust, low latency 100 Gb/s point-to-point link with minimal programmable logic overhead geared towards the needs of data acquisition systems with interleaved streaming requirements.