Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform

TL;DR

Eventor is a specialized FPGA-based accelerator that significantly improves the energy efficiency of event-based monocular multi-view stereo processing, enabling real-time 3D reconstruction on embedded systems.

Contribution

The paper introduces a novel FPGA accelerator for EMVS, optimizing critical stages and reformulating algorithms for hardware efficiency, achieving high throughput and low power consumption.

Findings

Up to 24x energy efficiency improvement over CPU

Real-time EMVS processing on FPGA

Effective hardware-friendly algorithm reformulation

Abstract

Event cameras are bio-inspired vision sensors that asynchronously represent pixel-level brightness changes as event streams. Event-based monocular multi-view stereo (EMVS) is a technique that exploits the event streams to estimate semi-dense 3D structure with known trajectory. It is a critical task for event-based monocular SLAM. However, the required intensive computation workloads make it challenging for real-time deployment on embedded platforms. In this paper, Eventor is proposed as a fast and efficient EMVS accelerator by realizing the most critical and time-consuming stages including event back-projection and volumetric ray-counting on FPGA. Highly paralleled and fully pipelined processing elements are specially designed via FPGA and integrated with the embedded ARM as a heterogeneous system to improve the throughput and reduce the memory footprint. Meanwhile, the EMVS algorithm is reformulated to a more hardware-friendly manner by rescheduling, approximate computing and hybrid data quantization. Evaluation results on DAVIS dataset show that Eventor achieves up to $24\times$ improvement in energy efficiency compared with Intel i5 CPU platform.