Temperature mapping of stacked silicon dies from x-ray diffraction intensities

TL;DR

This paper introduces a non-invasive x-ray diffraction method to map temperature distributions within stacked silicon dies in 3D integrated circuits, overcoming limitations of traditional surface techniques.

Contribution

The authors develop and demonstrate a novel x-ray diffraction technique using the Debye-Waller factor for 3D temperature mapping of silicon dies in stacks.

Findings

Achieved 3 K temperature resolution for silicon dies.

Spatial resolution of 100 um x 400 um.

Temporal resolution of 20 seconds.

Abstract

Increasing power densities in integrated circuits has led to an increased prevalence of thermal hotspots in integrated circuits. Tracking these thermal hotspots is imperative to prevent circuit failures. In 3D integrated circuits, conventional surface techniques like infrared thermometry are unable to measure 3D temperature distribution and optical and magnetic resonance techniques are difficult to apply due to the presence of metals and large current densities. X-rays offer high penetration depth and can be used to probe 3D structures. We report a method utilizing the temperature dependence of x-rays diffraction intensity via the Debye-Waller factor to simultaneously map the temperature of an individual silicon die that is a part of a stack of dies. Utilizing beamline 1-ID-E at the Advanced Photon Source (Argonne), we demonstrate for each individual silicon die, a temperature resolution of 3 K, a spatial resolution of 100 um x 400 um and a temporal resolution of 20 s. Utilizing a sufficiently high intensity laboratory source, e.g., from a liquid anode source, this method can be scaled down to laboratories for non-invasive temperature mapping of 3D integrated circuits.