CoMeFa: Compute-in-Memory Blocks for FPGAs
Aman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus, Hanindhito, Jaydeep Kulkarni, Lizy K. John

TL;DR
This paper introduces CoMeFa, a modification of FPGA block RAMs to enable compute-in-memory capabilities, significantly boosting compute density and performance for applications like deep learning.
Contribution
The paper proposes practical CoMeFa RAM architectures for FPGAs that integrate compute and storage, enhancing efficiency without requiring SRAM technology changes.
Findings
CoMeFa RAMs increase FPGA compute density substantially.
Adding CoMeFa RAMs yields up to 2.5x speedup in benchmarks.
CoMeFa RAMs are versatile for diverse parallel applications.
Abstract
Block RAMs (BRAMs) are the storage houses of FPGAs, providing extensive on-chip memory bandwidth to the compute units implemented using Logic Blocks (LBs) and Digital Signal Processing (DSP) slices. We propose modifying BRAMs to convert them to CoMeFa (Compute-In-Memory Blocks for FPGAs) RAMs. These RAMs provide highly-parallel compute-in-memory by combining computation and storage capabilities in one block. CoMeFa RAMs utilize the true dual port nature of FPGA BRAMs and contain multiple programmable single-bit bit-serial processing elements. CoMeFa RAMs can be used to compute in any precision, which is extremely important for evolving applications like Deep Learning. Adding CoMeFa RAMs to FPGAs significantly increases their compute density. We explore and propose two architectures of these RAMs: CoMeFa-D (optimized for delay) and CoMeFa-A (optimized for area). Compared to existing…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Network Packet Processing and Optimization · Advanced Data Storage Technologies
