Design Considerations for 2D Dirac-Source FETs: Device Parameters, Non-Idealities and Benchmarking

TL;DR

This paper explores the design, non-idealities, and benchmarking of 2D Dirac-source FETs, providing insights into device parameters, performance impacts, and material choices for low-power applications.

Contribution

It offers a comprehensive analysis of key device parameters, non-idealities, and benchmarking strategies for 2D Dirac-source FETs using ballistic simulations.

Findings

Device parameters significantly affect performance.

Non-idealities like disorder impact device efficiency.

Benchmarking guides material selection for optimal performance.

Abstract

Dirac-source field-effect transistors (DS-FETs) have been proposed as promising candidates for low-power switching devices by leveraging the Dirac cone of graphene as a low-pass energy filter. In particular, using two-dimensional (2D) materials as the channel in a DS-FET is of interest for ultimate scaling purposes. In this paper, we investigate the design considerations for 2D DS-FETs using ballistic simulations based on Landauer formalism. We study the impact of several key device parameters on the device performance, such as graphene doping, Schottky barrier heights, and effective mass of the 2D channel. In addition, we study the impact of non-idealities on the performance of DS-FETs, such as graphene disorder and rethermalization, as well as ways to mitigate them. Finally, we benchmark the performance of DS-FETs for different channel materials, providing a guide for the proper choice of material for 2D DS-FETs.