Image Classification on Accelerated Neural Networks

TL;DR

This paper presents an FPGA-based acceleration design for a basic CNN model's training and inference phases, significantly improving performance over existing deep learning platforms.

Contribution

It introduces a novel FPGA implementation that accelerates CNN training and inference, focusing on the fully connected layer and demonstrating substantial performance gains.

Findings

FPGA design outperforms TensorFlow on host computer by approximately 2 times

Training of convolutional layer is not included, focusing on fully connected layer acceleration

Performance improvements are observed in both training and inference phases

Abstract

For image classification problems, various neural network models are commonly used due to their success in yielding high accuracies. Convolutional Neural Network (CNN) is one of the most frequently used deep learning methods for image classification applications. It may produce extraordinarily accurate results with regard to its complexity. However, the more complex the model is the longer it takes to train. In this paper, an acceleration design that uses the power of FPGA is given for a basic CNN model which consists of one convolutional layer and one fully connected layer for the training phase of the fully connected layer. Nonetheless, inference phase is also accelerated automatically due to the fact that training phase includes inference. In this design, the convolutional layer is calculated by the host computer and the fully connected layer is calculated by an FPGA board. It should be noted that the training of convolutional layer is not taken into account in this design and is left for future research. The results are quite encouraging as this FPGA design tops the performance of some of the state-of-the-art deep learning platforms such as Tensorflow on the host computer approximately 2 times in both training and inference.