Towards integrating hardware Data Plane acceleration in Network Functions Virtualization

TL;DR

This paper introduces a framework that integrates hardware data plane acceleration into NFV architectures, enhancing packet processing flexibility and performance through custom hardware switches programmed with P4.

Contribution

It presents a novel integration of hardware data plane acceleration within ETSI NFV architecture using P4-programmed switches and open source VIMs and MANO tools.

Findings

Enhanced packet processing flexibility with custom algorithms.

Improved network performance through dedicated hardware execution.

Successful integration within existing NFV architecture.

Abstract

This paper proposes a framework for integrating data plane (DP) acceleration within the Network Functions Virtualization (NFV) architecture. Data plane programming (DPP) proves to be beneficial for NFV environments, as it provides full packet forwarding flexibility through the use of self-designed algorithms. Additionally, DPP provides high-performance networking, as the DP can be configured to execute specific functions on dedicated hardware. We present an integration of the DP acceleration within the ETSI NFV architecture that leverages custom DP functions implemented in hardware switches using P4 language. Besides, OpenStack and Kubernetes are used as Virtualized Infrastructure Managers (VIMs) and Open Source MANO (OSM) as the Management and Orchestration (MANO) element.