Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics

TL;DR

This paper presents an automated tool flow that translates domain-specific tensor expressions into high-performance FPGA accelerators with high-bandwidth memory, specifically optimized for computational fluid dynamics applications.

Contribution

It introduces an MLIR-based compiler and hardware generation flow that automates the creation of FPGA accelerators with specialized memory architectures from high-level tensor specifications.

Findings

Achieved up to 103 GFLOPS performance on CFD applications.

FPGA implementation is up to 25x more energy-efficient than CPU solutions.

Successfully generated systems with efficient data movement and high parallelism.

Abstract

Numerical simulations can help solve complex problems. Most of these algorithms are massively parallel and thus good candidates for FPGA acceleration thanks to spatial parallelism. Modern FPGA devices can leverage high-bandwidth memory technologies, but when applications are memory-bound designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. This development process requires hardware design skills that are uncommon in domain-specific experts. In this paper, we propose an automated tool flow from a domain-specific language (DSL) for tensor expressions to generate massively-parallel accelerators on HBM-equipped FPGAs. Designers can use this flow to integrate and evaluate various compiler or hardware optimizations. We use computational fluid dynamics (CFD) as a paradigmatic example. Our flow starts from the high-level specification of tensor operations and combines an MLIR-based compiler with an in-house hardware generation flow to generate systems with parallel accelerators and a specialized memory architecture that moves data efficiently, aiming at fully exploiting the available CPU-FPGA bandwidth. We simulated applications with millions of elements, achieving up to 103 GFLOPS with one compute unit and custom precision when targeting a Xilinx Alveo U280. Our FPGA implementation is up to 25x more energy-efficient than expert-crafted Intel CPU implementations.