FPGA-extended General Purpose Computer Architecture

TL;DR

This paper proposes a novel CPU architecture integrating small FPGAs within the ISA to enable custom instructions, improve memory bandwidth, and support software-transparent context-switching, with promising simulation results.

Contribution

It introduces a new architecture combining FPGAs with CPUs for customizable instructions and evaluates its feasibility and performance benefits.

Findings

Simulation shows performance close to fully enabled instruction cores.

Feasibility demonstrated through FPGA prototyping and opcode miss analysis.

Architecture addresses main memory bandwidth challenges in high-end CPUs.

Abstract

This paper introduces a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). Small FPGAs inside a general-purpose processor (CPU) can be used effectively to implement custom or standardised instructions. Our proposed architecture directly address related challenges for high-end CPUs, where such highly-integrated FPGAs would have the highest impact, such as on main memory bandwidth. This also enables software-transparent context-switching. The simulation-based evaluation of a dynamically reconfigurable core shows promising results approaching the performance of an equivalent core with all enabled instructions. Finally, the feasibility of adopting the proposed architecture in today's CPUs is studied through the prototyping of fast-reconfigurable FPGAs and studying the miss behaviour of opcodes.