Improved Analysis of Current-Steering DACs Using Equivalent Timing Errors

TL;DR

This paper presents an improved analysis method for current-steering DACs that accounts for timing errors, leading to more accurate predictions of signal distortion and insights into partially-segmented architectures.

Contribution

It introduces a more precise behavioral simulation model using equivalent timing error analysis for current-steering DACs, enhancing accuracy over previous methods.

Findings

Analysis significantly more accurate than prior models

Timing mismatch impacts SDR in partially-segmented DACs

Behavioral simulation reveals effects of timing errors on nonlinear distortion

Abstract

Current-steering (CS) digital-to-analog converters (DACs) generate analog signals by combining weighted current sources. Ideally, the current sources are combined at each switching instant simultaneously. However, this is not true in practice due to timing mismatch, resulting in nonlinear distortion. This work uses the equivalent timing error model, introduced by previous work, to analyze the signal-to-distortion ratio (SDR) resulting from these timing errors. Using a behavioral simulation model we demonstrate that our analysis is significantly more accurate than the previous methods. We also use our simulation model to investigate the effect of timing mismatch in partially-segmented CS-DACs, i.e., those comprised of both equally-weighted and binary-weighted current sources.