Pinning Fault Mode Modeling for DWM Shifting

TL;DR

This paper models how fabrication imperfections in notches cause pinning faults in domain wall memories, affecting reliability and predicting fault rates based on geometric variations.

Contribution

It introduces a model for pinning faults caused by non-uniform notch variations and analyzes their impact on DW memory fault rates.

Findings

Pinning fault rate predicted at 10^-8 per shift.

Variation in notch geometry increases critical shift current.

Estimated mean-time-to-failure is approximately 2 seconds.

Abstract

Extreme scaling for purposes of achieving higher density and lower energy continues to increase the probability of memory faults. For domain wall (DW) memories, misalignment faults arise when aligning domains with access points. A previously understudied type of shifting fault, a pinning fault may occur due to non-uniform pinning potential distribution caused by notches with fabrication imperfections. This non-uniformity can pin a wall during current-induced DW motion. This paper provides a model of geometric variations varying width, depth, and curvature variations of a notch, their impacts on the critical shift current, and a study of the resulting impact on fault rates of DW memory systems. An increase in the effective critical shift current due to 5% variation predicts a pinning fault rate on the order of $10^{-8}$ per shift, which results in a mean-time-to-failure of circa 2s for a DW memory system.