Towards sub-30nm Contacted Gate Pitch, Forked Contact and Dynamically-Doped Nanosheets to Enhance Si and 2D Materials Device Scaling

TL;DR

This paper introduces a novel Forked-Contacts, Dynamically-Doped Multigate transistor design that significantly enhances device scaling for Si and 2D materials, achieving sub-30-nm contact pitches and a 10 nm scaling boost.

Contribution

It presents a new transistor architecture with advanced simulation validation, enabling superior device performance at aggressive nanoscale dimensions.

Findings

Achieved sub-30-nm contact pitches with improved device characteristics.

Demonstrated a 10 nm scaling boost over existing nanosheet MOSFETs.

Validated device performance using atomistic-simulation fundamentals.

Abstract

We propose a novel Forked-Contacts, Dynamically-Doped Multigate transistor as ultimate scaling booster for both Si and 2D materials in aggressively-scaled nanosheet devices. Using accurate dissipative DFT-NEGF atomistic-simulation fundamentals and cell layout extrinsics, we demonstrate superior and optimal device characteristics and invertor energy - delays down to sub-30-nm pitches, i.e., a 10 nm scaling boost compared to the nanosheet MOSFET references.