Cross-Layer Approximation For Printed Machine Learning Circuits

TL;DR

This paper introduces a novel cross-layer approximation approach for printed electronics to enable complex machine learning models like MLPs and SVMs, achieving significant area and power savings with minimal accuracy loss.

Contribution

It presents the first integration of approximate computing with printed electronics design for ML, combining algorithmic and circuit-level approximations to optimize performance.

Findings

Achieves 47% area reduction in ML models

Achieves 44% power reduction in ML models

Maintains less than 1% accuracy loss

Abstract

Printed electronics (PE) feature low non-recurring engineering costs and low per unit-area fabrication costs, enabling thus extremely low-cost and on-demand hardware. Such low-cost fabrication allows for high customization that would be infeasible in silicon, and bespoke architectures prevail to improve the efficiency of emerging PE machine learning (ML) applications. However, even with bespoke architectures, the large feature sizes in PE constraint the complexity of the ML models that can be implemented. In this work, we bring together, for the first time, approximate computing and PE design targeting to enable complex ML models, such as Multi-Layer Perceptrons (MLPs) and Support Vector Machines (SVMs), in PE. To this end, we propose and implement a cross-layer approximation, tailored for bespoke ML architectures. At the algorithmic level we apply a hardware-driven coefficient approximation of the ML model and at the circuit level we apply a netlist pruning through a full search exploration. In our extensive experimental evaluation we consider 14 MLPs and SVMs and evaluate more than 4300 approximate and exact designs. Our results demonstrate that our cross approximation delivers Pareto optimal designs that, compared to the state-of-the-art exact designs, feature 47% and 44% average area and power reduction, respectively, and less than 1% accuracy loss.