TL;DR
ArithsGen is a versatile arithmetic circuit generator that creates customizable, hierarchical, and multi-format circuits, improving upon existing tools by supporting complex architectures and enabling better optimization for hardware accelerators.
Contribution
We developed ArithsGen, a new generator supporting complex, hierarchical arithmetic circuits with multiple output formats, enhancing customization and optimization capabilities over existing tools.
Findings
Generated circuits improve hardware design tradeoffs
Initial circuit choice affects approximate implementation quality
Supported multiple output formats for diverse applications
Abstract
Generators of arithmetic circuits can automatically deliver various implementations of arithmetic circuits that show different tradeoffs between the key circuit parameters (delay, area, power consumption). However, existing (freely-)available generators are limited if more complex circuits with a hierarchical structure and additional architecture optimization are requested. Furthermore, they support only a few output formats. In order to overcome the above-mentioned limitations, we developed a new generator of arithmetic circuits called ArithsGen. ArithsGen can generate specific architectures of signed and unsigned adders and multipliers using basic building elements such as wires and gates. Compared to existing generators, the user can, for example, specify the type of adders used in multipliers. The tool supports various outputs formats (Verilog, BLIF, C/C++, or integer netlists).…
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