Post-Fabrication Trimming of Silicon Photonic Ring Resonators at Wafer-Scale

TL;DR

This paper presents a low-cost, wafer-scale post-fabrication trimming technique for silicon photonic ring resonators, enabling precise resonance tuning to improve manufacturability and practical application viability.

Contribution

It introduces a novel Ge implant and localized thermal annealing method for resonance wavelength correction at wafer-scale, addressing fabrication variability issues.

Findings

Resonance wavelength trimmed within +/-32 pm of target

Demonstrated wafer-scale tuning across a 300 mm SOI wafer

Enables high-volume manufacturing of silicon photonic devices

Abstract

Silicon ring resonator-based devices, such as modulators, detectors, filters, and switches, play important roles in integrated photonic circuits for optical communication, high-performance computing, and sensing applications. However, the high sensitivity to fabrication variations has limited their volume manufacturability and commercial adoption. Here, we report a low-cost post-fabrication trimming method to tune the resonance wavelength of a silicon ring resonator and correct for fabrication variations at wafer-scale. We use a Ge implant to create an index trimmable section in the ring resonator and an on-chip heater to apply a precise and localized thermal annealing to tune and set its resonance to a desired wavelength. We demonstrate resonance wavelength trimming of ring resonators fabricated across a 300 mm silicon-on-insulator (SOI) wafer to within +/-32 pm of a target wavelength of 1310 nm, providing a viable path to high-volume manufacturing and opening up new practical applications for these devices.