AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications
Jawad Haj Yahya, Haris Volos, Davide B. Bartolini, Georgia Antoniou,, Jeremie S. Kim, Zhe Wang, Kleovoulos Kalaitzidis, Tom Rollet, Zhirui Chen, Ye, Geng, Onur Mutlu, Yiannakis Sazeides

TL;DR
AgileWatts introduces a novel deep C-state architecture that significantly reduces energy consumption in datacenter server processors for latency-sensitive applications by minimizing wake-up latency and power leakage.
Contribution
This work presents a new deep C-state design with hardware modifications that eliminate context save/restore and cache flush latencies, achieving substantial energy savings with minimal performance impact.
Findings
Up to 71% energy reduction in Memcached workloads
Average 35% energy savings with 1% performance degradation
Effective deep C-state management for latency-sensitive datacenter applications
Abstract
User-facing applications running in modern datacenters exhibit irregular request patterns and are implemented using a multitude of services with tight latency requirements. These characteristics render ineffective existing energy conserving techniques when processors are idle due to the long transition time from a deep idle power state (C-state). While prior works propose management techniques to mitigate this inefficiency, we tackle it at its root with AgileWatts (AW): a new deep C-state architecture optimized for datacenter server processors targeting latency-sensitive applications. AW is based on three key ideas. First, AW eliminates the latency overhead of saving/restoring the core context (i.e., micro-architectural state) when powering-off/-on the core in a deep idle power state by i) implementing medium-grained power-gates, carefully distributed across the CPU core, and ii)…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Cloud Computing and Resource Management · Interconnection Networks and Systems
