Efficient Placement and Migration Policies for an STT-RAM based Hybrid L1 Cache for Intermittently Powered Systems
SatyaJaswanth Badri, Mukesh Saini, Neeraj Goel

TL;DR
This paper introduces efficient placement and migration policies for a hybrid SRAM and STT-RAM cache in intermittently powered systems, significantly reducing write energy and improving performance.
Contribution
It proposes novel placement and migration strategies for hybrid caches that minimize STT-RAM writes and enhance energy efficiency in energy-harvesting, intermittently powered devices.
Findings
STT-RAM writes reduced from 63.35% to 35.93%.
Performance improved by 32.85%.
Energy consumption decreased by 23.42%.
Abstract
The number of battery-powered devices is rapidly increasing due to the widespread use of IoT-enabled nodes in various fields. Energy harvesters, which help to power embedded devices, are a feasible alternative to replacing battery-powered devices. In a capacitor, the energy harvester stores enough energy to power up the embedded device and compute the task. This type of computation is referred to as intermittent computing. Energy harvesters are unable to supply continuous power to embedded devices. All registers and cache in conventional processors are volatile. We require a Non-Volatile Memory (NVM)-based Non-Volatile Processor (NVP) that can store registers and cache contents during a power failure. NVM-based caches reduce system performance and consume more energy than SRAM-based caches. This paper proposes Efficient Placement and Migration policies for hybrid cache architecture…
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Taxonomy
TopicsEnergy Harvesting in Wireless Networks · Advanced Memory and Neural Computing · Caching and Content Delivery
