Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations

TL;DR

This paper experimentally demonstrates a resilient RRAM-based in-memory computing system capable of 16 parallel operations and introduces the first RRAM-based multi-level-cell 2-bit adder, overcoming device variability and endurance challenges.

Contribution

It presents the first experimental implementation of multi-level-cell RRAM in-memory computing with high parallelism and endurance, advancing the practical application of RRAM in IMC.

Findings

Successfully demonstrated 16 parallel RRAM-based in-memory logic operations.

First experimental realization of RRAM-based multi-level-cell 2-bit adder.

Achieved strong resilience to device variability and endurance issues.

Abstract

Crossbar arrays of resistive memories (RRAM) hold the promise of enabling In-Memory Computing (IMC), but essential challenges due to the impact of device imperfection and device endurance have yet to be overcome. In this work, we demonstrate experimentally an RRAM-based IMC logic concept with strong resilience to RRAM variability, even after one million endurance cycles. Our work relies on a generalization of the concept of in-memory Scouting Logic, and we demonstrate it experimentally with up to 16 parallel devices (operands), a new milestone for RRAM in-memory logic. Moreover, we combine IMC with Multi-Level-Cell programming and demonstrate experimentally, for the first time, an IMC RRAM-based MLC 2-bit adder.