A 915-1220 TOPS/W Hybrid In-Memory Computing based Image Restoration and Region Proposal Integrated Circuit for Neuromorphic Vision Sensors in 65nm CMOS

TL;DR

This paper introduces a hybrid in-memory computing circuit in 65nm CMOS that significantly enhances energy efficiency for image restoration and region proposal in neuromorphic vision sensors.

Contribution

It proposes a novel 11-transistor hybrid SRAM-DRAM cell and an improved region proposal algorithm for high-performance, energy-efficient neuromorphic vision processing.

Findings

Achieved up to 1220 TOPS/W energy efficiency for image restoration.

Demonstrated 915 TOPS/W energy efficiency for combined image restoration and region proposal.

Developed a robust region proposal algorithm for improved performance.

Abstract

In this work, we present a hybrid memory bit cell - collocated SRAM and DRAM (CRAM) consisting of 11 transistors for in-memory computing (IMC) based image restoration (IR) and region proposal (RP). A robust RP updated algorithm is proposed to improve the performance. This work demonstrates IMC based global parallel diffusion and column/row-wise projection to achieve a maximal energy efficiency of 1220 TOPS/W for image restoration and 915 TOPS/W when combined with region proposal.