In-memory Associative Processors: Tutorial, Potential, and Challenges

TL;DR

This paper provides a comprehensive overview of in-memory associative processors, discussing their functionalities, recent trends, applications, limitations, and future challenges in the context of overcoming von Neumann bottlenecks.

Contribution

It offers a detailed tutorial on associative processors, highlighting recent developments, implementation technologies, and potential applications, along with discussing current challenges and future research directions.

Findings

Associative processors enable data-centric computation reducing memory-processor communication.

Recent trends show high-density memories revitalizing APs for data-intensive tasks.

Challenges include technological limitations and scalability issues.

Abstract

In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which highly reduces the memory-processor communications during computation. Hence, significant speedup and energy savings could be achieved especially with data-intensive applications. Associative processors (APs) were proposed in the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, we overview the functionalities and recent trends of APs in addition to the implementation of each content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges, and future directions are discussed.