A hardware-software co-design approach to minimize the use of memory resources in multi-core neuromorphic processors

TL;DR

This paper introduces a hardware-software co-design method inspired by biological neural networks to reduce memory usage in multi-core neuromorphic processors, including optimized routing schemes and resource allocation algorithms.

Contribution

It presents a novel co-design framework with new routing schemes and a hardware-aware placement algorithm tailored for neuromorphic computing.

Findings

Validated routing scheme with small-world networks

Preliminary results on resource optimization for derived networks

Guidelines for application-specific neuromorphic chip design

Abstract

Both in electronics and biology, physical implementations of neural networks have severe energy and memory constraints. We propose a hardware-software co-design approach for minimizing the use of memory resources in multi-core neuromorphic processors, by taking inspiration from biological neural networks. We use this approach to design new routing schemes optimized for small-world networks and to provide guidelines for designing novel application-specific multi-core neuromorphic chips. Starting from the hierarchical routing scheme proposed, we present a hardware-aware placement algorithm that optimizes the allocation of resources for arbitrary network models. We validate the algorithm with a canonical small-world network and present preliminary results for other networks derived from it.