Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview
Junchi Yan, Xianglong Lyu, Ruoyu Cheng, Yibo Lin

TL;DR
This paper reviews recent advances in applying machine learning techniques to the complex placement and routing tasks in chip design, highlighting potential benefits and future research directions.
Contribution
It provides a comprehensive overview of machine learning methods for placement and routing, comparing them with traditional approaches and discussing future challenges.
Findings
Machine learning offers scalable solutions for placement and routing.
Deep learning methods outperform traditional heuristics in some benchmarks.
Challenges include data availability and integration into existing workflows.
Abstract
Placement and routing are two indispensable and challenging (NP-hard) tasks in modern chip design flows. Compared with traditional solvers using heuristics or expert-well-designed algorithms, machine learning has shown promising prospects by its data-driven nature, which can be of less reliance on knowledge and priors, and potentially more scalable by its advanced computational paradigms (e.g. deep networks with GPU acceleration). This survey starts with the introduction of basics of placement and routing, with a brief description on classic learning-free solvers. Then we present detailed review on recent advance in machine learning for placement and routing. Finally we discuss the challenges and opportunities for future research.
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Taxonomy
TopicsVLSI and FPGA Design Techniques · 3D IC and TSV technologies · VLSI and Analog Circuit Testing
