Demonstrating BrainScaleS-2 Inter-Chip Pulse-Communication using EXTOLL

TL;DR

This paper demonstrates inter-chip pulse communication for the BrainScaleS-2 neuromorphic system using EXTOLL networking, enabling scalable neural network modeling across multiple chips with high bandwidth and low latency.

Contribution

It introduces a pulse-routing implementation and software extensions for BSS-2 to facilitate inter-chip communication using EXTOLL technology.

Findings

Successful implementation of high-bandwidth inter-chip pulse routing

Demonstration of feed-forward pulse-routing on BSS-2

Extensions to BSS-2 software stack for inter-chip communication

Abstract

The BrainScaleS-2 (BSS-2) Neuromorphic Computing System currently consists of multiple single-chip setups, which are connected to a compute cluster via Gigabit-Ethernet network technology. This is convenient for small experiments, where the neural networks fit into a single chip. When modeling networks of larger size, neurons have to be connected across chip boundaries. We implement these connections for BSS-2 using the EXTOLL networking technology. This provides high bandwidths and low latencies, as well as high message rates. Here, we describe the targeted pulse-routing implementation and required extensions to the BSS-2 software stack. We as well demonstrate feed-forward pulse-routing on BSS-2 using a scaled-down version without temporal merging.