Faster Born probability estimation via gate merging and frame optimisation

TL;DR

This paper introduces gate merging and frame optimisation techniques that improve classical estimation of quantum circuit outcome probabilities by reducing sampling overhead, applicable to various circuit types and outperforming prior methods as non-Clifford gates increase.

Contribution

The paper presents novel polynomial-scaling classical sub-routines for circuit representation optimisation, reducing negativity overhead in quantum probability estimation.

Findings

Improved negativity scaling in random circuits with Clifford+$T$ and Haar-random gates.

Methods outperform prior quasi-probability simulators with increasing non-Clifford gates.

Applicable to general circuits regardless of gate sets or frame representations.

Abstract

Outcome probability estimation via classical methods is an important task for validating quantum computing devices. Outcome probabilities of any quantum circuit can be estimated using Monte Carlo sampling, where the amount of negativity present in the circuit frame representation quantifies the overhead on the number of samples required to achieve a certain precision. In this paper, we propose two classical sub-routines: circuit gate merging and frame optimisation, which optimise the circuit representation to reduce the sampling overhead. We show that the runtimes of both sub-routines scale polynomially in circuit size and gate depth. Our methods are applicable to general circuits, regardless of generating gate sets, qudit dimensions and the chosen frame representations for the circuit components. We numerically demonstrate that our methods provide improved scaling in the negativity overhead for all tested cases of random circuits with Clifford+$T$ and Haar-random gates, and that the performance of our methods compares favourably with prior quasi-probability simulators as the number of non-Clifford gates increases.