A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model

TL;DR

This paper introduces a compact drain current model for SRAM in sub/near-threshold voltages, enabling accurate failure probability estimation with significantly reduced data requirements compared to traditional Monte Carlo simulations.

Contribution

It proposes a new drain current model and analytical failure probability models for SRAM at low voltages, improving accuracy and efficiency over existing methods.

Findings

Models achieve less than 11% error at 0.5V VDD.

Data sample size is 43.6 times smaller than state-of-the-art.

Validated across different voltages and temperatures.

Abstract

Sub/Near-threshold static random-access memory (SRAM) design is crucial for addressing the memory bottleneck in energy-constrained applications. However, the high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a rare event in memory circuits, the time and storage overhead of conventional Monte Carlo (MC) simulations cannot be tolerated. On the other hand, classic analytical methods predicting failure probabilities from a physical expression become inaccurate in the sub/near-threshold region due to the assumed distribution or the oversimplified drain current model for nanoscale devices. This work first proposes a simple but efficient drain current model to describe the drain-induced barrier lowering effect at low voltages. Based on that, the probability density functions of the interest metrics in SRAM are derived. Two analytical models are then put forward to evaluate SRAM dynamic stabilities including access and write-time failures. The proposed models can be extended easily to different types of SRAM with different read/write assist circuits. The models are validated against MC simulations across different operating voltages and temperatures. The average relative errors at 0.5V VDD are only 8.8% and 10.4% for the access-time and write failure models respectively. The size of required data samples is 43.6X smaller than that of the state-of-the-art method.