Lightweight Soft Error Resilience for In-Order Cores

TL;DR

Turnpike is a co-designed compiler and architecture scheme that provides lightweight soft error resilience for in-order cores, significantly reducing performance overhead compared to existing methods.

Contribution

It introduces a novel approach combining compiler optimizations and microarchitectural support to bypass unnecessary error verification, achieving low overhead in soft error resilience.

Findings

Average 0-14% runtime overhead with Turnpike

Outperforms state-of-the-art with 29-84% overhead

Effective in 36 benchmark tests

Abstract

Acoustic-sensor-based soft error resilience is particularly promising, since it can verify the absence of soft errors and eliminate silent data corruptions at a low hardware cost. However, the state-of-the-art work incurs a significant performance overhead for in-order cores due to frequent structural/data hazards during the verification. To address the problem, this paper presents Turnpike, a compiler/architecture co-design scheme that can achieve lightweight yet guaranteed soft error resilience for in-order cores. The key idea is that many of the data computed in the core can bypass the soft error verification without compromising the resilience. Along with simple microarchitectural support for realizing the idea, Turnpike leverages compiler optimizations to further reduce the performance overhead. Experimental results with 36 benchmarks demonstrate that Turnpike only incurs a 0-14% run-time overhead on average while the state-of-the-art incurs a 29-84% overhead when the worst-case latency of the sensor based error detection is 10-50 cycles.