Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes

TL;DR

This paper introduces generalized post-processors inspired by simulated annealing techniques to significantly reduce error floors in LDPC codes, enhancing decoding performance with minimal additional complexity.

Contribution

It proposes a novel, generalized post-processor design based on simulated annealing concepts, effectively lowering error floors in structured LDPC codes.

Findings

Error floors reduced by two orders of magnitude

Effective for structured LDPC codes like IEEE 802.11n

Minimal overhead added to belief-propagation decoders

Abstract

The error floor phenomenon, associated with iterative decoders, is one of the most significant limitations to the applications of low-density parity-check (LDPC) codes. A variety of techniques from code design to decoder implementation have been proposed to address the error floor problem, among which post-processors have shown to be both effective and implementation-friendly. In this work, we take the inspiration from simulated annealing to generalize the post-processor design using three methods: quenching, extended heating, and focused heating, each of which targets a different error structure. The resulting post-processor is demonstrated to lower the error floors by two orders of magnitude for two structured code examples, a (2209, 1978) array LDPC code, and a (1944, 1620) LDPC code used by the IEEE 802.11n standard. The post-processor can be integrated to a belief-propagation decoder with minimal overhead. The post-processor design is equally applicable to other structured LDPC codes.