High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder

TL;DR

This paper introduces the first hardware architecture for nonbinary SCL polar decoding, achieving high throughput and efficiency through a split-tree algorithm and parallel sub-decoders, suitable for practical applications.

Contribution

It presents a novel high-throughput hardware decoder for nonbinary polar codes using a split-tree approach, significantly improving throughput and efficiency over direct-mapped designs.

Findings

Achieves 26.1 Mb/s throughput with a 28nm CMOS prototype.

Outperforms direct-mapped decoder by over 10x in throughput.

Maintains excellent error-correction performance.

Abstract

Nonbinary polar codes defined over Galois field GF(q) have shown improved error-correction performance than binary polar codes using successive-cancellation list (SCL) decoding. However, nonbinary operations are complex and a direct-mapped decoder results in a low throughput, representing difficulties for practical adoptions. In this work, we develop, to the best of our knowledge, the first hardware implementation for nonbinary SCL polar decoding. We present a high-throughput decoder architecture using a split-tree algorithm. The sub-trees are decoded in parallel by smaller sub-decoders with a reconciliation stage to maintain constraints between sub-trees. A skimming algorithm is proposed to reduce the reconciliation complexity for further improved throughput. The split-tree nonbinary SCL (S-NBSCL) polar decoder is prototyped using a 28nm CMOS technology for a (128,64) polar code over GF(256). The decoder delivers 26.1 Mb/s throughput, 11.65 Mb/s/mm$^2$ area efficiency and 28.8 nJ/b energy efficiency, outperforming the direct-mapped decoder by 10.3x, 4.4x and 2.7x, respectively, while achieving excellent error-correction performance.