Fault-tolerance in qudit circuit design

TL;DR

This paper examines how the choice of entangling gates and network topology, rather than circuit depth alone, influences error spread and failure rates in qudit quantum circuits, proposing error mitigation strategies.

Contribution

It challenges the focus on circuit depth in fault-tolerance, highlighting the combined impact of gate choice and topology on error propagation in qudit circuits.

Findings

Circuit depth is not the main factor in error spread.

Gate choice and topology significantly influence failure rates.

Selective resource application can mitigate errors in linear-depth circuits.

Abstract

The efficient decomposition of multi-controlled gates is a significant factor in quantum compiling, both in circuit depth and T-gate count. Recent work has demonstrated that qudits have the potential to reduce resource requirements from linear to logarithmic depth and to avoid fractional phase rotations. Here we argue, based on the scaling of decoherence in high-index states, that circuit depth is not the primary factor, and that both the choice of entangling gate and interaction network topology act together to determine the spread of errors and ultimate failure rate in a circuit. We further show that for certain linear-depth circuits, additional error mitigation is possible via selective application of resources.