Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout

TL;DR

This paper introduces a memory layout technique and compiler pass that enable burst transfers in FPGA accelerators, significantly increasing memory bandwidth and reducing I/O bottlenecks for compute-intensive kernels.

Contribution

It proposes a novel memory allocation method and compiler support to facilitate burst-friendly data layouts, improving memory throughput in FPGA accelerators.

Findings

Memory throughput increases with burst-friendly layout

Minimal logic overhead introduced by the technique

Potential for exploiting additional parallelism

Abstract

Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the accelerator's effective performance. Techniques enabling data reuse, such as tiling, lower the pressure on memory traffic but still often leave the accelerators I/O-bound. A further increase in effective bandwidth is possible by using burst rather than element-wise accesses, provided the data is contiguous in memory. In this paper, we propose a memory allocation technique, and provide a proof-of-concept source-to-source compiler pass, that enables such burst transfers by modifying the data layout in external memory. We assess how this technique pushes up the memory throughput, leaving room for exploiting additional parallelism, for a minimal logic overhead.