Response of a Commercial 0.25 um Thin-Film Silicon-on-Sapphire CMOS Technology to Total Ionizing Dose

TL;DR

This study evaluates the radiation tolerance of a 0.25 um silicon-on-sapphire CMOS technology, showing minimal threshold voltage shifts and leakage current increases under ionizing radiation, indicating suitability for high-radiation environments.

Contribution

It provides detailed characterization of the radiation response of silicon-on-sapphire CMOS technology at both device and circuit levels, demonstrating its robustness for use in particle physics experiments.

Findings

Threshold voltage change <170 mV at 100 krad(SiO2)

Leakage current change <1 nA at 100 krad(SiO2)

Power supply current increase <5% under radiation

Abstract

The radiation response of a 0.25 um silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. Device-level characterization showed threshold voltage change of less than 170 mV and leakage current change of less than 1 nA for individual nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power supply current at the circuit level was less than 5%, consistent with the small change in off-state transistor leakage current. The technology exhibits good characteristics for use in the electronics of the ATLAS experiment at the Large Hadron Collider.