A 4.9-GHz Low Power, Low Jitter, LC Phase Locked Loop

TL;DR

This paper introduces a low power, low jitter LC PLL designed in 0.25-um CMOS technology, achieving 1.3 ps random jitter, 7.5 ps deterministic jitter, and a tuning range of 4.6 to 5.0 GHz.

Contribution

It presents a novel low power, low jitter LC PLL with detailed analysis and fabrication in a commercial CMOS process, addressing tuning range limitations.

Findings

Random jitter of 1.3 ps

Deterministic jitter of 7.5 ps

Power consumption of 111 mW at 4.9 GHz

Abstract

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-um Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has been investigated and traced to the first stage of the divider chain. The power consumption at the central frequency is 111 mW.