Devitalizing noise-driven instability of entangling logic in silicon devices with bias controls

TL;DR

This paper investigates how bias controls can mitigate charge noise effects on entangling quantum logic in silicon quantum dots, providing practical device design strategies to enhance noise robustness without sacrificing operation speed.

Contribution

It introduces a computational approach to optimize device engineering for noise-robust CNOT gates in silicon quantum dots, a novel strategy for improving quantum processor reliability.

Findings

Bias control strategies significantly improve noise robustness.

Device design guidelines enable high-fidelity entangling operations.

Almost no speed loss in optimized CNOT operations.

Abstract

The quality of quantum bits (qubits) in silicon is highly vulnerable to charge noise that is omni-present in semiconductor devices and is in principle hard to be suppressed. For a realistically sized quantum dot system based on a silicon-germanium heterostructure whose confinement is manipulated with electrical biases imposed on top electrodes, we computationally explore the noise-robustness of 2-qubit entangling operations with a focus on the controlled-X (CNOT) logic that is essential for designs of gate-based universal quantum logic circuits. With device simulations based on the physics of bulk semiconductors augmented with electronic structure calculations, we not only quantify the degradation in fidelity of single-step CNOT operations with respect to the strength of charge noise, but also discuss a strategy of device engineering that can significantly enhance noise-robustness of CNOT operations with almost no sacrifice of speed compared to the single-step case. Details of device designs and controls that this work presents can establish a rare but practical guideline for potential efforts to secure silicon-based quantum processors using an electrode-driven quantum dot platform.