A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-$\mu$m with 0.1-nA PTAT and 1.1-$\mu$A CWT 38-ppm/$^\circ$C Designs

TL;DR

This paper introduces a family of simple, low-power current references based on 2T voltage references, demonstrating high stability and accuracy in 0.18-μm SOI technology, with potential for scaled CMOS implementation.

Contribution

It presents a novel family of current references using a 2T voltage reference and a single transistor buffer, offering simplicity and robustness against PVT variations.

Findings

Achieved 0.096-nA PTAT current with low line sensitivity and temperature coefficient.

Demonstrated 1.09-μA CWT current with high stability and low variability.

Validated portability to advanced CMOS technologies through simulations.

Abstract

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18-$\mu$m partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant-$g_m$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/$^\circ$C, and a variability $(\sigma/\mu)$ of 1.66 %. Then, two 4T+1R $\mu$A-range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09-$\mu$A (resp. 0.99-$\mu$A) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/$^\circ$C (resp. 290-ppm/$^\circ$C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma/\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations.