Low-Power Silicon Strain Sensor Based on CMOS Current Reference Topology

TL;DR

This paper presents a low-power silicon strain sensor using CMOS current reference topology, achieving high sensitivity and tunability through innovative circuit design verified by experiments.

Contribution

It introduces a novel CMOS-based strain sensor leveraging a Widlar current source topology with enhanced sensitivity and temperature compensation capabilities.

Findings

Achieved a strain sensitivity of 2.54 nA/μϵ with a basic circuit.

Enhanced the design to reach 12.02 nA/μϵ sensitivity with active tuning.

Maintained low power consumption between 20 and 150 μW.

Abstract

A strain sensor inspired by a Widlar self-biased current source topology called $\beta$-multiplier is developed to obtain a strain-dependent reference current with high supply rejection. The sensor relies on the piezoresistive effect in the silicon MOS transistors that form the current reference circuit. The device behavior is analytically computed and verified with experimental measurements under four-point bending test. A basic implementation with an integrated resistor reaches a strain sensitivity of 2.54 nA/$\mu\epsilon$ (gauge factor of 324) for a temperature sensitivity of 52.06 nA/{\deg}C. A more advanced full-transistor circuit based on current subtraction principle is furthered implemented in order to reach strain sensitivity up to 12.02 nA/$\mu\epsilon$ (gauge factor of 1773) and temperature sensitivity of -28.72 nA/{\deg}C. This implementation includes a CMOS active load to tune the strain and temperature sensitivities with a total power consumption between 20 and 150 $\mu$W.