Evaluating Persistent Memory Range Indexes: Part Two [Extended Version]

TL;DR

This paper evaluates and compares recent persistent memory range indexes on real hardware, revealing that newer designs often do not outperform older ones and identifying key challenges and future research directions.

Contribution

It provides a comprehensive experimental evaluation of state-of-the-art PM range indexes on real hardware and offers new design principles and future directions.

Findings

Newer PM indexes inherit past techniques but do not always outperform older proposals.

PM indexes are competitive with DRAM-optimized indexes, suggesting unified design potential.

Challenges remain in supporting variable-length keys and managing NUMA effects.

Abstract

Scalable persistent memory (PM) has opened up new opportunities for building indexes that operate and persist data directly on the memory bus, potentially enabling instant recovery, low latency and high throughput. When real PM hardware (Intel Optane DCPMM) first became available, previous work evaluated PM indexes proposed in the pre-Optane era. Since then, newer indexes based on real PM have appeared, but it is unclear how they compare to each other and to previous proposals, and what further challenges remain. This paper addresses these issues by analyzing and experimentally evaluating state-of-the-art PM range indexes built for real PM. We find newer designs inherited past techniques with new improvements, but they do not necessarily outperform pre-Optane era proposals. Moreover, PM indexes are often also very competitive or even outperform indexes tailored for DRAM, highlighting the potential of using a unified design for both PM and DRAM. Functionalitywise, these indexes still lack good support for variable-length keys and handling NUMA effect. Based on our findings, we distill new design principles and highlight future directions.